Semiconductor manufacturers have been trying for decades to fit an ever-increasing number of transistors onto a limited chip area. However, as transistors became smaller and smaller, the industry approached the physical limits of the classical two-dimensional increase in the number of packed transistors.
IBM now introduces the nanostack, a new architecture that allows transistors to be built in three dimensions. Instead of expanding only along the X and Y axes, the chips get the ability to scale along the Z axis, that is, to stack elements vertically.
The principle is reminiscent of the construction of a modern city. When there is no more space to expand on the surface, buildings grow higher and on the same basis provide a significantly larger usable area. IBM applies the same logic to chips, stacking silicon wafers and transistors on top of each other.
According to IBM data, the nanostack enables almost twice as many transistors per unit area compared to the nanosheet technology used in IBM’s 2 nm class chips. A chip the size of a fingernail could fit almost 100 billion transistors.
Initial estimates show that such chips could consume up to 70 percent less energy than existing 2 nm solutions, with an increase in speed of up to 50 percent. This would enable faster training and execution of AI models, longer autonomy of laptops and phones, as well as lower device consumption at the same level of performance.
What is a nanostack?
Basically, a nanostack is a set of vertically stacked nanosheet transistors. IBM introduced nanosheet technology in 2017 as the successor to FinFET construction. By using GAA transistors, where the gate surrounds the channel from all sides, denser packing is possible with reduced “leakage” of electrical energy.
Nanostack, however, is not just a simple stacking of existing nanosheet elements. One of the key innovations is the ability to place n-type and p-type transistors one above the other, instead of next to each other.
IBMThese two types of transistors use differently doped semiconductor materials. In n-type, conduction is dominated by negatively charged electrons, while p-type uses so-called cavities, i.e. positive charge carriers.
By physically separating them, IBM gets the ability to choose the material that best suits its characteristics for each type. Previously, the choice of material represented a compromise, because a solution that suited one type of transistor was not necessarily optimal for another.
The transistors in the nanostack architecture are not placed directly above each other, but in an alternating arrangement that resembles a brick wall. Such a construction additionally increases the density, but requires completely new production techniques.
Why is a new transistor architecture needed?
As the spacing between transistors decreases, it becomes increasingly difficult to place n-type and p-type elements close enough due to the different materials they are made of. Instead of further converging in the same plane, IBM therefore stacks them vertically.
The company expects that the nanostack could extend the scaling of logic chips well into 2040. The technology would thus enable continued development despite approaching atomic dimensions, where the traditional reduction of elements becomes more and more complex.
Vertical construction also brings new problems. The first is the precise alignment and evenness of the silicon wafers that connect to each other. A very thin dielectric oxide layer is used between the layers, which should limit parasitic capacitance and electrical resistance.
Another challenge is connecting the transistors. Lines are becoming smaller and smaller and have to connect elements arranged on multiple levels. IBM therefore relies on advanced lithography techniques, including High NA EUV equipment from ASML.
Power supply from the back of the chip
Nanostack also uses power supply from the back side of the silicon wafer, while signals are transmitted from the front side. This approach, known as backside power delivery, frees up additional space and enables higher transistor density.
According to IBM, nanostack could provide up to 40 percent more memory directly on the chip. The simultaneous separation of n-type and p-type transistors allows manufacturers to experiment more freely with new materials and adapt each layer to the desired performance.
In order for the nanostack to reach mass production, it is necessary to further improve the materials for thermally conductive bonding layers, processing of the back side of the wafer, three-dimensional quality control and software tools for designing 3D chips.
IBM and its partners are now working on these technologies to prepare the nanostack architecture for wider application in industry. Instead of asking how many transistors can fit on a flat surface, the next phase of chip development will be based on how many can be safely and efficiently stacked on top of each other, IBM explains.